NEC PD78052 - Page 27

27
LIST OF FIGURES (3/8)
Figure No. Title Page
8-23. Timing of Pulse Width Measurement Operation by Free-Running Counter and
Two Capture Registers (with Rising Edge Specified) .................................................................... 202
8-24. Control Register Settings for Pulse Width Measurement by Means of Restart ............................. 203
8-25. Timing of Pulse Width Measurement Operation by Means of Restart
(with Rising Edge Specified) ......................................................................................................... 203
8-26. Control Register Settings in External Event Counter Mode .......................................................... 204
8-27. External Event Counter Configuration Diagram ............................................................................ 205
8-28. External Event Counter Operation Timings (with Rising Edge Specified) ..................................... 205
8-29. Control Register Settings in Square-Wave Output Mode .............................................................. 206
8-30. Square-Wave Output Operation Timing ........................................................................................ 207
8-31. Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger............. 208
8-32. Timing of One-Shot Pulse Output Operation Using Software Trigger ........................................... 209
8-33. Control Register Settings for One-Shot Pulse Output Operation Using External Trigger.............. 210
8-34. Timing of One-Shot Pulse Output Operation Using External Trigger
(With Rising Edge Specified)......................................................................................................... 211
8-35. 16-Bit Timer Register Start Timing ................................................................................................ 212
8-36. Timings After Change of Compare Register During Timer Count Operation ................................. 212
8-37. Capture Register Data Retention Timing....................................................................................... 213
8-38. Operation Timing of OVF0 Flag..................................................................................................... 214
9-1. 8-Bit Timer/Event Counters 1 and 2 Block Diagram ...................................................................... 221
9-2. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 .......................................... 222
9-3. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 .......................................... 222
9-4. Timer Clock Select Register 1 Format........................................................................................... 224
9-5. 8-Bit Timer Mode Control Register 1 Format................................................................................. 225
9-6. 8-Bit Timer Output Control Register Format .................................................................................. 226
9-7. Port Mode Register 3 Format ........................................................................................................ 227
9-8. Interval Timer Operation Timings .................................................................................................. 228
9-9. External Event Counter Operation Timings (with Rising Edge Specified) ..................................... 231
9-10. Square-Wave Output Operation Timing ........................................................................................ 233
9-11. Interval Timer Operation Timing .................................................................................................... 234
9-12. External Event Counter Operation Timings (with Rising Edge Specified) ..................................... 236
9-13. Square-Wave Output Operation Timing ........................................................................................ 238
9-14. 8-Bit Timer Registers 1 and 2 Start Timing.................................................................................... 238
9-15. Event Counter Operation Timing ................................................................................................... 239
9-16. Timing after Compare Register Change during Timer Count Operation ....................................... 239
10-1. Watch Timer Block Diagram .......................................................................................................... 243
10-2. Timer Clock Select Register 2 Format........................................................................................... 244
10-3. Watch Timer Mode Control Register Format ................................................................................. 245
11-1. Watchdog Timer Block Diagram .................................................................................................... 249
11-2. Timer Clock Select Register 2 Format........................................................................................... 251
11-3. Watchdog Timer Mode Register Format........................................................................................ 252