NEC PD78052 - Page 31

31
LIST OF FIGURES (7/8)
Figure No. Title Page
19-12. 3-Wire Serial I/O Mode Timing ...................................................................................................... 472
19-13. Circuit of Switching in Transfer Bit Order ...................................................................................... 473
19-14. Reception Completion Interrupt Request Generation Timing (when ISRM = 1)............................ 474
19-15. Receive Buffer Register Read Disable Period .............................................................................. 475
20-1. Real-time Output Port Block Diagram ........................................................................................... 478
20-2. Real-time Output Buffer Register Configuration ............................................................................ 479
20-3. Port Mode Register 12 Format ...................................................................................................... 480
20-4. Real-time Output Port Mode Register Format ............................................................................... 480
20-5. Real-time Output Port Control Register Format ............................................................................ 481
21-1. Basic Configuration of Interrupt Function ...................................................................................... 486
21-2. Interrupt Request Flag Register Format ........................................................................................ 489
21-3. Interrupt Mask Flag Register Format............................................................................................. 490
21-4. Priority Specify Flag Register Format............................................................................................ 491
21-5. External Interrupt Mode Register 0 Format ................................................................................... 492
21-6. External Interrupt Mode Register 1 Format ................................................................................... 493
21-7. Sampling Clock Select Register Format........................................................................................ 494
21-8. Noise Eliminator Input/Output Timing (during rising edge detection) ............................................ 495
21-9. Program Status Word Configuration ............................................................................................. 496
21-10. Flowchart of Generation from Non-Maskable Interrupt Request to Acknowledgment................... 498
21-11. Non-Maskable Interrupt Request Acknowledge Timing................................................................. 498
21-12. Non-Maskable Interrupt Request Acknowledge Operation ........................................................... 499
21-13. Interrupt Request Acknowledge Processing Algorithm.................................................................. 501
21-14. Interrupt Request Acknowledge Timing (Minimum Time) .............................................................. 502
21-15. Interrupt Request Acknowledge Timing (Maximum Time) ............................................................. 502
21-16. Multiple Interrupt Example............................................................................................................. 504
21-17. Interrupt Request Hold .................................................................................................................. 506
21-18. Basic Configuration of Test Function ............................................................................................. 507
21-19. Format of Interrupt Request Flag Register 1L ............................................................................... 508
21-20. Format of Interrupt Mask Flag Register 1L.................................................................................... 508
21-21. Key Return Mode Register Format................................................................................................ 509
22-1. Memory Map when Using External Device Expansion Function ................................................... 512
22-2. Memory Expansion Mode Register Format ................................................................................... 516
22-3. Memory Size Switching Register Format ...................................................................................... 517
22-4. Instruction Fetch from External Memory ....................................................................................... 519
22-5. External Memory Read Timing ...................................................................................................... 520
22-6. External Memory Write Timing ...................................................................................................... 521
22-7. External Memory Read Modify Write Timing ................................................................................. 522
22-8. Connection Example of
µ PD78054 and Memory .......................................................................... 523
23-1. Oscillation Stabilization Time Select Register Format ................................................................... 526
23-2. HALT Mode Clear upon Interrupt Request Generation ................................................................. 528