334
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
µ
PD78054 Subseries)
(1) Register setting
The 2-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface
control register (SBIC), and the interrupt timing specify register (SINT).
(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSIM0 to 00H.
Notes 1. Bit 6 (COI) is a read-only bit.
2. Can be used freely as port function.
3. Be sure to set WUP to 0 when the 2-wire serial I/O mode.
4. When CSIE0=0, COI becomes 0.
Remark × : don’t care
PM×× : Port mode register
P×× : Port output latch
<6><5>43210<7>
Symbol
CSIM0 CSIE0 COI WUP
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIM01
0
1
Serial Interface Channel 0 Clock Selection
Input Clock to SCK0 pin from off-chip
8-bit timer register 2 (TM2) output
R/W
1 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
CSIM
04
0
CSIM00
×
0
1
FF60H 00H R/W
Note 1
Address After Reset R/W
R/W
CSIM
03
CSIM
02
PM25 P25 PM26 P26
PM27
P27
Operation
Mode
Start Bit
SIO/SB0/P25
Pin Function
SO0/SB1/P26
Pin Function
SCK0/P27
Pin Function
×
10
WUP
0
1
Wake-up Function Control
Interrupt request signal generation with each serial transfer in any mode
Interrupt request signal generation when the address received after bus release
(when CMDD=RELD=1) matches the slave address register (SVA) data in SBI mode
R/W
2-wire serial
l/O mode
0
1
11
×
0
×
0
0
×
0
×
0
0
1
1
Note 2 Note 2
Note 2 Note 2
MSB
P25 (CMOS
input/output
SB0 (N-ch
open-drain
input/output)
SB1 (N-ch
open-drain
input/output)
P26 (CMOS
input/output)
3-wire Serial I/O mode (See Section 16.4.2, “3-wire serial I/O mode operation”
SBI mode (See section 16.4.3, “SBI mode operation”
Note 3
COI
0
Slave Address Comparison Result Flag
Note 4
Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data
Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
R
1
CSIE0
0
Serial Interface Channel 0 Operation Control
Operation stopped
Operation enabled
R/W
1
SCK0 (N-ch
open-drain
input/output)
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