NEC PD78052 - Page 34

34
LIST OF TABLES (2/3)
Table No. Title Page
9-8. 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges .............................................. 232
9-9. Interval Times when 2-Channel 8-Bit Timer/ Event Counters (TM1 and TM2) are Used
as 16-Bit Timer/Event Counter ...................................................................................................... 235
9-10. Square-Wave Output Ranges when 2-Channel 8-Bit Timer/ Event Counters (TM1 and TM2)
are Used as 16-Bit Timer/Event Counter....................................................................................... 237
10-1. Interval Timer Interval Time ........................................................................................................... 241
10-2. Watch Timer Configuration ............................................................................................................ 242
10-3. Interval Timer Interval Time ........................................................................................................... 246
11-1. Watchdog Timer Runaway Detection Times.................................................................................. 247
11-2. Interval Times ................................................................................................................................ 248
11-3. Watchdog Timer Configuration ...................................................................................................... 249
11-4. Watchdog Timer Runaway Detection Times.................................................................................. 253
11-5. Interval Timer Interval Time ........................................................................................................... 254
12-1. Clock Output Control Circuit Configuration ................................................................................... 256
13-1. Buzzer Output Control Circuit Configuration ................................................................................. 261
14-1. A/D Converter Configuration ......................................................................................................... 265
15-1. D/A Converter Configuration ......................................................................................................... 282
16-1. Differences between Channels 0, 1, and 2 ................................................................................... 287
16-2. Serial Interface Channel 0 Configuration ...................................................................................... 290
16-3. Various Signals in SBI Mode ......................................................................................................... 323
17-1. Differences between Channels 0, 1, and 2 ................................................................................... 341
17-2. Serial Interface Channel 0 Configuration ...................................................................................... 344
17-3. Serial Interface Channel 0 Interrupt Request Signal Generation .................................................. 347
17-4. Signals in I
2
C Bus Mode................................................................................................................ 376
18-1. Serial Interface Channel 1 Configuration ...................................................................................... 394
18-2. Interval Timing Through CPU Processing (when the internal clock is operating).......................... 436
18-3. Interval Timing Through CPU Processing (when the external clock is operating)......................... 437
19-1. Serial Interface Channel 2 Configuration ...................................................................................... 440
19-2. Serial Interface Channel 2 Operating Mode Settings .................................................................... 446
19-3. Relation between Main System Clock and Baud Rate .................................................................. 450
19-4. Relation between ASCK Pin Input Frequency and Baud Rate
(When BRGC is set to 00H) .......................................................................................................... 451
19-5. Relation between Main System Clock and Baud Rate .................................................................. 459
19-6. Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)......... 460