NEC PD78052 - Page 566

566
CHAPTER 27 INSTRUCTION SET
Clock Flag
Note 1 Note 2
ZACCY
A, #byte 2 4 – A, CY ← A – byte ×××
saddr, #byte 3 6 8 (saddr), CY ← (saddr) – byte ×××
A, r
Note 3
2 4 – A, CY ← A – r ×××
r, A 2 4 – r, CY ← r – A ×××
A, saddr 2 4 5 A, CY ← A – (saddr) ×××
A, !addr16 3 8 9 + n A, CY ← A – (addr16) ×××
A, [HL] 1 4 5 + n A, CY ← A – (HL) ×××
A, [HL + byte] 2 8 9 + n A, CY ← A – (HL + byte) ×××
A, [HL + B] 2 8 9 + n A, CY ← A – (HL + B) ×××
A, [HL + C] 2 8 9 + n A, CY ← A – (HL + C) ×××
A, #byte 2 4 – A, CY ← A – byte – CY ×××
saddr, #byte 3 6 8 (saddr), CY ← (saddr) – byte – CY ×××
A, r
Note 3
2 4 – A, CY ← A – r – CY ×××
r, A 2 4 – r, CY ← r – A – CY ×××
A, saddr 2 4 5 A, CY ← A – (saddr) – CY ×××
A, !addr16 3 8 9 + n A, CY ← A – (addr16) – CY ×××
A, [HL] 1 4 5 + n A, CY ← A – (HL) – CY ×××
A, [HL + byte] 2 8 9 + n A, CY ← A – (HL + byte) – CY ×××
A, [HL + B] 2 8 9 + n A, CY ← A – (HL + B) – CY ×××
A, [HL + C] 2 8 9 + n A, CY ← A – (HL + C) – CY ×××
A, #byte 2 4 – A ← A ∧ byte ×
saddr, #byte 3 6 8 (saddr) ← (saddr) byte ×
A, r
Note 3
24 –A ← A ∧ r ×
r, A 2 4 – r ← r ∧ A ×
A, saddr 2 4 5 A ← A ∧ (saddr) ×
A, !addr16 3 8 9 + n A ← A ∧ (addr16) ×
A, [HL] 1 4 5 + n A ← A ∧ (HL) ×
A, [HL + byte] 2 8 9 + n A ← A ∧ (HL + byte) ×
A, [HL + B] 2 8 9 + n A ← A ∧ (HL + B) ×
A, [HL + C] 2 8 9 + n A ← A ∧ (HL + C) ×
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access.
2. When an area except the internal high-speed RAM area is accessed.
3. Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
CPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
Mnemonic Operands Byte Operation
Instruction
Group
SUB
SUBC
AND
8-bit
operation