37
Specifications Section 2-1
Programming language Ladder diagram
Instruction length 1 step per instruction, 1 to 5 words per instruction
Instructions Basic instructions: 14
Special instructions: 105 instructions, 185 variations
Execution time Basic instructions: 0.64 µs (LD instruction)
Special instructions: 7.8 µs (MOV instruction)
Program capacity 4,096 words
Max. I/O
capacity
CPU Unit only 10 points 20 points 32 points
With Expansion
I/O Units and
Expansion Units
170 points max. 180 points max. 192 points max.
Input bits IR 00000 to IR 00915 (Words not used for input bits can be used for work bits.)
Output bits IR 01000 to IR 01915 (Words not used for output bits can be used for work bits.)
Work bits 928 bits: IR 02000 to IR 04915 and IR 20000 to IR 22715
Special bits (SR area) 448 bits: SR 22800 to SR 25515
Temporary bits (TR area) 8 bits (TR0 to TR7)
Holding bits (HR area) 320 bits: HR 0000 to HR 1915 (Words HR 00 to HR 19)
Auxiliary bits (AR area) 384 bits: AR 0000 to AR 2315 (Words AR 00 to AR 23)
Link bits (LR area) 256 bits: LR 0000 to LR 1515 (Words LR 00 to LR 15)
Timers/Counters 256 timers/counters (TIM/CNT 000 to TIM/CNT 255)
1-ms timers: TMHH(−−)
10-ms timers: TIMH(15)
100-ms timers: TIM
1-s/10-s timers: TIML(−−)
Decrementing counters: CNT
Reversible counters: CNTR(12)
Data memory Read/Write: 2,048 words (DM 0000 to DM 2047)*
Read-only: 456 words (DM 6144 to DM 6599)
PC Setup: 56 words (DM 6600 to DM 6655)
*The Error Log is contained in DM 2000 to DM 2021.
Interrupt processing 2 interrupts 4 interrupts 4 interrupts
Shared by the external interrupt inputs (counter mode) and the quick-response inputs.
Interval timer interrupts 1 (Scheduled Interrupt Mode or Single Interrupt Mode)
High-speed counter One high-speed counter: 20 kHz single-phase or 5 kHz two-phase (linear count method)
Counter interrupt: 1 (set value comparison or set-value range comparison)
Interrupt Inputs
(Counter mode)
2 inputs 4 inputs 4 inputs
Shared by the external interrupt inputs and the quick-response inputs.
Pulse output Two points with no acceleration/deceleration, 10 Hz to 10 kHz each, and no direction control.
One point with trapezoid acceleration/deceleration, 10 Hz to 10 kHz, and direction control.
Two points with variable duty-ratio outputs.
(Pulse outputs can be used with transistor outputs only, they cannot be used with relay out-
puts.)
Synchronized pulse control One point:
A pulse output can be created by combining the high-speed counter with pulse outputs and
multiplying the frequency of the input pulses from the high-speed counter by a fixed factor.
(This output is possible with transistor outputs only, it cannot be used with relay outputs.)
Quick-response inputs 2 inputs 4 inputs 4 inputs
Shared by the external interrupt inputs and the interrupt inputs (counter mode).
Min. input pulse width: 50 µs max.
Input time constant
(ON response time =
OFF response time)
Can be set for all input points.
(1 ms, 2 ms, 3 ms, 5 ms, 10 ms, 20 ms, 40 ms, or 80 ms)
Item CPU Unit Specification
10 I/O points
(relay/transistor outputs)
20 I/O points
(relay/transistor outputs)
32 I/O points
(transistor outputs)