Panasonic FP0H - Page 36

Settings of Control Unit
4-6
 Allocation of I/O relating to pulse output control (Only in FPΣ compatible instruction
mode)
• By using the special data register DT90052 by the pulse output control instruction (F0),
operations such as loading the near home input and stopping the pulse output forcibly can
be performed.
FP0H mode
FP
Σ
mode
bit no.
15 4 3 1 0
Software reset
0 0 0 1 0 0 0 0
8 7
0: Disable 1: Enable
H1: Fixed
Count
0: Enable 1: Disable
Pulse output
0: Continue 1: Stop
Near home input
0: Invalid 1: Valid
Channel specification
H0 to H3: CH0 to CH3
bit no.
15 43210
Near home input
Reset input setting
0: Valid, 1: Invalid
High-speed counter instruction clear
pulse output stop
0: Continue, 1: Clear, stop
Channel specification
H0, H2: CH0, CH2
Software reset
0: Disable, 1: Enable
Count
0: Enable 1: Disable
0: Invalid, 1:Valid
• When controlling the above functions using external inputs, arbitrary inputs can be allocated.
The following program is for loading the near home input of CH1 using the input X10.
X10
DT90052H1110
F0 MV
DT90052H1100
F0 MV
（ ）
DF
KEY POINTS
• In the FPΣ compatible instruction mode, the allocations of J-point control
and limit inputs are not available.
• In the FPΣ compatible instruction mode, the allocations of system stop,
error clear request, deceleration stop and J-point speed change are not
available.
REFERENCE
For details of the FPΣ mode, refer to "11. FPΣ Mode".