Panasonic FP0H

Settings of Control Unit
4-8
4.1.4 When Using High-speed Counter Function
• The following reserved areas are allocated to the hardware reset input and control active flag.
 Allocation of I/O signals (When using internal input)
FP0H mode
Signal name
I/O number
CH0 CH1 CH2 CH3
Count input
Single-phase input X0 X1 X3 X4
2-phase input X0/X1 - X3/X4 -
Hardware reset
input
Single-phase input
X2 X2 X5 X5
2-phase input
X2 - X5 -
Control active flag
(BUSY)
Single-phase input
R9110 R9111 R9112 R9113
2-phase input
R9110 - R9112 -
FPΣ mode
Signal name
I/O number
CH0
CH1
CH2
CH3
Count input
Single-phase input X0 X1 X3 X4
2-phase input X0/X1 - X3/X4 -
Hardware reset
input
Single-phase input
X2 X2 X5 X5
2-phase input
X2 - X5 -
Control active flag
(BUSY)
Single-phase input
R903A R903B R903C R903D
2-phase input
R903A - R903C -
(Note 1): When the reset input settings of reset input for the single-phase input overlap at CH0 and CH1 or CH2 and
CH3, the setting of CH0 or CH2 has priority.