RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1151
Dec 10, 2015
SFERE bit (sync field error detection enable bit)
The SFERE bit enables or disables detection of the sync field error.
With 0 set, the sync field error is not detected.
With 1 set, the sync field error is detected.
Upon detection of the sync field error, the system is placed in the next header wait state, irrespective of the setting of this
bit.
When this bit is set to 1, the detection result is indicated in the SFER flag in the LESTn register.
For details of the sync field error, refer to 17.4.6 Error Status.
IPERE bit (ID parity error detection enable bit)
The IPERE bit enables or disables detection of the ID parity error.
With 0 set, the ID parity error is not detected.
With 1 set, the ID parity error is detected.
When this bit is set to 1, the detection result is indicated in the IPER flag in the LESTn register.
For details of the ID parity error, refer to 17.4.6 Error Status.
LTES bit (timeout error select bit)
The LTES bit selects the specific timeout function to be used.
With 0 set, the timeout function applies to frame timeout.
With 1 set, the timeout function applies to response timeout.
For details of the timeout error, refer to 17.4.6 Error Status.
To Next Page
Loading...
