Renesas RL78/F13 - CAN Receive FIFO Pointer Control Register M (Rfpctrm) (M = 0, 1)

RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1329
Dec 10, 2015
18.3.36 CAN Receive FIFO Pointer Control Register m (RFPCTRm) (m = 0, 1)
Address RFPCTR0L: F0348H, RFPCTR0H: F0349H
RFPCTR1L: F034AH, RFPCTR1H: F034BH
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — — RFPC[7:0]
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 to 8 — Reserved The write value should always be 0. R
7 to 0 RFPC[7:0] Receive FIFO Pointer When these bits are set to H'FF, the read pointer moves to
the next unread message in the receive FIFO buffer. The
setting for these bits must be H’FF.
W
• RFPC[7:0] Bits
When the RFPC[7:0] bits are set to H'FF, the read pointer moves to the next unread message in the receive
FIFO buffer. At this time, the RFMC[5:0] (receive FIFO unread message counter) value in the RFSTSm register
is decremented. Read the RFIDLm, RFIDHm, RFTSm, RFPTRm, and RFDF0m to RFDF3m registers to read
messages in the receive FIFO buffer, and then write H'FF to the RFPC[7:0] bits.
Write H'FF to these bits when the RFE bit in the RFCCm register is set to 1 (receive FIFO buffers are used) and
the RFEMP flag in the RFSTSm register is 0 (the receive FIFO buffer contains unread messages).