RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1344
Dec 10, 2015
18.3.48 CANi Transmit/Receive FIFO Pointer Control Register k (CFPCTRk) (i = 0) (k = 0)
Address CFPCTR0L: F035CH
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — — CFPC[7:0]
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 to 8 — Reserved The write value should always be 0. R
7 to 0 CFPC[7:0] CANi Transmit/Receive FIFO
Pointer
Receive mode:
Writing H'FF to these bits moves the read pointer to the
next unread message in the transmit/receive FIFO buffer.
Transmit mode:
Writing H'FF to these bits moves the write pointer to the
next stage of the transmit/receive FIFO buffer.
W
• CFPC[7:0] Bits
Receive mode (CFM [1:0] value in the CFCCHk register is B'00):
Writing H'FF to the CFPC[7:0] bits moves the read pointer to the next unread message in the transmit/receive
FIFO buffer. At this time, the CFMC[5:0] value (transmit/receive FIFO message counter) in the CFSTSk register
is decremented. Read the CFIDLk, CFIDHk, CFTSk, CFPTRk, and CFDF0k to CFDF3k registers to read
messages in the transmit/receive FIFO buffer, and then write H'FF to the CFPC[7:0] bits.
Write H'FF to these bits when the CFE bit in the CFCCLk register is set to 1 (transmit/receive FIFO buffers are
used) and the CFEMP flag in the CFSTSk register is cleared to 0 (the transmit/receive FIFO buffer contains
messages).
Transmit mode (CFM [1:0] value in the CFCCHk register is B'01):
Writing H'FF to the CFPC[7:0] bits stores the data written to the CFIDLk, CFIDHk, CFPTRk, and CFDF0k to
CFDF3k registers in the transmit/receive FIFO buffer and moves the write pointer to the next stage of the
transmit/receive FIFO buffer. At this time, the CFMC[5:0] value is incremented. Write transmit messages to the
CFIDLk, CFIDHk, CFPTRk, and CFDF0k to CFDF3k registers and then write H'FF to the CFPC[7:0] bits.
Write H'FF to these bits when the CFE bit in the CFCCLk register is set to 1 and the CFFLL flag in the CFSTSk
register is cleared to 0 (the transmit/receive FIFO buffer is not full).
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