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Renesas RL78/F13 - CAN Receive Rule Entry Register Jal (Gaflidlj) (J = 0 to 15)

Renesas RL78/F13
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RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1309
Dec 10, 2015
18.3.18 CAN Receive Rule Entry Register jAL (GAFLIDLj) (j = 0 to 15)
Address GAFLIDL0L: F03A0H, GAFLIDL0H: F03A1H GAFLIDL1L: F03ACH, GAFLIDL1H: F03ADH
GAFLIDL2L: F03B8H, GAFLIDL2H: F03B9H GAFLIDL3L: F03C4H, GAFLIDL3H: F03C5H
GAFLIDL4L: F03D0H, GAFLIDL4H: F03D1H GAFLIDL5L: F03DCH, GAFLIDL5H: F03DDH
GAFLIDL6L: F03E8H, GAFLIDL6H: F03E9H GAFLIDL7L: F03F4H, GAFLIDL7H: F03F5H
GAFLIDL8L: F0400H, GAFLIDL8H: F0401H GAFLIDL9L: F040CH, GAFLIDL9H: F040DH
GAFLIDL10L: F0418H, GAFLIDL10H: F0419H GAFLIDL11L: F0424H, GAFLIDL11H: F0425H
GAFLIDL12L: F0430H, GAFLIDL12H: F0431H GAFLIDL13L: F043CH, GAFLIDL13H: F043DH
GAFLIDL14L: F0448H, GAFLIDL14H: F0449H GAFLIDL15L: F0454H, GAFLIDL15H: F0455H
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
GAFLID[15:0]
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 to 0 GAFLID[15:0] ID Set L Set the ID of the receive rule.
For the standard ID, set the ID in bits 10 to 0 and set bits
15 to 11 to 0.
R/W
Modify the GAFLIDLj register only when the RPAGE bit in the GRWCR register is set to 0 in global reset mode.
GAFLID[15:0] Bits
These bits are used to set the ID field of the receive rule. The ID value set by these bits is compared with the ID
in the received message during the acceptance filter processing.

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