RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS
R01UH0368EJ0210 Rev.2.10 320
Dec 10, 2015
4.3.2 Port registers (Pxx)
These registers set the output latch value of a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is
read
Note
.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Even when PMxx is set to 0 (output mode), the pin level can be read from Pxx by setting PMS.0 (port mode select) to
1.
Reset signal generation clears these registers to 00H.
Note When P33, P34, P70 to P74, P80 to P87, P90 to P97, P100 to P105, P120, and P125 are set up as analog
inputs of the A/D converter, P80 is set up as D/A converter output, or P81 to P85 are set up as analog inputs of
the comparator, if a port is read while in the input mode, 0 is always returned, not the pin level.
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