RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1307
Dec 10, 2015
18.3.16 CAN Timestamp Register (GTSC)
Address GTSC: F032EH
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
TS[15:0]
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Description Counter Value R/W
15 to 0 TS[15:0] The timestamp counter value can be read. H'0000 to H'FFFF R
• TS[15:0] Bits
When the TS[15:0] bits are read, the read value shows the timestamp counter (16-bit free-running counter)
value at that time. The TS[15:0] value is captured when the SOF is detected and then stored in the receive
buffer or the FIFO buffer. The timestamp counter is initialized in global reset mode.
The timestamp counter start timing and stop timing depend on the count source.
• When the TSSS value in the GCFGL register is 0 (the clock obtained by frequency-dividing f
CLK by 2 (fCLK/2) is
selected):
The timestamp counter starts counting when the CAN module has transitioned to global operating mode.
This counter stops counting when the CAN module has transitioned to global stop mode or global test mode.
• When the TSSS value in the GCFGL register is 1 (CANi bit time clock is selected):
The timestamp counter starts counting when the corresponding channel has transitioned to channel
communication mode.
This counter stops counting when the corresponding channel has transitioned to channel reset mode
or channel halt mode.
To Next Page
Loading...
