Renesas RL78/F13 - Cani Transmit;Receive FIFO Control Register Kl (Cfcclk) (I = 0) (K = 0)

RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1338
Dec 10, 2015
18.3.45 CANi Transmit/Receive FIFO Control Register kL (CFCCLk) (i = 0) (k = 0)
Address CFCCL0L: F0350H, CFCCL0H: F0351H
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
CFIGCV[2:0] CF
IM
— CFDC[2:0] — — — — — CF
TXIE
CF
RXIE
CF
E
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 to 13 CFIGCV[2:0] Transmit/Receive FIFO Receive
Interrupt Request Timing Select
b15 b14 b13
0 0 0 : When FIFO is 1/8 full.
0 0 1 : When FIFO is 2/8 full.
0 1 0 : When FIFO is 3/8 full.
0 1 1 : When FIFO is 4/8 full.
1 0 0 : When FIFO is 5/8 full.
1 0 1 : When FIFO is 6/8 full.
1 1 0 : When FIFO is 7/8 full.
1 1 1 : When FIFO is full.
R/W
12 CFIM Transmit/Receive FIFO Interrupt
Source Select
0:
• Receive mode
When the number of received messages has met the
condition set by the CFIGCV[2:0] bits, a FIFO receive
interrupt request is generated.
• Transmit mode
When the buffer becomes empty upon completion of
message transmission, a FIFO transmit interrupt
request is generated.
1:
• Receive mode
A FIFO receive interrupt request is generated each
time a message has been received.
• Transmit mode
A FIFO transmit interrupt request is generated each
time a message has been transmitted.
R/W
11 — Reserved This bit is always read as 0. The write value should
always be 0.
R
10 to 8 CFDC[2:0] Transmit/Receive FIFO Buffer
Depth
Configuration
b10 b9 b8
0 0 0 : 0 messages
0 0 1 : 4 messages
0 1 0 : 8 messages
0 1 1 : 16 messages
1 0 0 : Setting prohibited
1 0 1 : Setting prohibited
1 1 0 : Setting prohibited
1 1 1 : Setting prohibited
R/W
7 to 3 — Reserved These bits are always read as 0. The write value should
always be 0.
R
2 CFTXIE Transmit/Receive FIFO Transmit
Interrupt Enable
0: Transmit/receive FIFO transmit interrupt is disabled.
1: Transmit/receive FIFO transmit interrupt is enabled.
R/W
1 CFRXIE Transmit/Receive FIFO Receive
Interrupt Enable
0: Transmit/receive FIFO receive interrupt is disabled.
1: Transmit/receive FIFO receive interrupt is enabled.
R/W
0 CFE Transmit/Receive FIFO Buffer
Enable
0: No transmit/receive FIFO buffer is used.
1: Transmit/receive FIFO buffers are used.
R/W