EasyManua.ls Logo

Renesas RL78/F13 - Page 1371

Renesas RL78/F13
1879 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1339
Dec 10, 2015
CFIGCV[2:0] Bits
These bits are used to specify the fraction of the transmit/receive FIFO buffer (the number of messages is
selected by the setting of the CFDC[2:0] bits) that must be filled for the FIFO buffer to generate a receive
interrupt request when the CFM[1:0] bits are set to B'00 (reception mode) and the CFIM bit is set to 0.
When the CFDC[2:0] bits are set to B'001 (4 messages), set the CFIGCV[2:0] bits to B'001, B'011, B'101, or
B'111.
Modify these bits only in global reset mode.
CFIM Bit
This bit is used to select a transmit/receive FIFO interrupt source. Modify this bit only in global reset mode.
CFDC[2:0] Bits
These bits are used to set the number of messages that can be stored in a single transmit/receive FIFO buffer.
If these bits are set to B'000, do not use any receive FIFO buffer. Modify these bits only in global reset mode.
CFTXIE Bit
When this bit is set to 1 and the CFTXIF flag in the CFSTSk register is set to 1, a transmit/receive FIFO transmit
interrupt request is generated.
Modify this bit with the CFE bit set to 0 (no transmit/receive FIFO buffer is used).
CFRXIE Bit
When this bit is set to 1 and the CFRXIF flag in the CFSTSk register is set to 1, a transmit/receive FIFO receive
interrupt request is generated.
Modify this bit with the CFE bit set to 0.
CFE Bit
Setting this bit to 1 makes transmit/receive FIFO buffers available.
When this bit is set to 0 in transmit mode, if a message in the transmit/receive FIFO buffer is being transmitted
or to be transmitted next, the transmit/receive FIFO buffer becomes empty after completion of transmission,
CAN bus error detection, or arbitration lost. In other cases or in receive mode, the transmit/receive FIFO buffer
becomes empty immediately.
This bit is cleared to 0 when the following conditions are met.
Receive mode: Global reset mode
Transmit mode: Channel reset mode
Modify this bit only in the following mode.
Receive mode: Global operating mode or global test mode
Transmit mode: Channel communication mode or channel halt mode

Table of Contents

Related product manuals