RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1401
Dec 10, 2015
18.9 RAM Window
The CAN area from H’F03A0 to H’F0681 consists of two windows. The RPAGE bit in the GRWCR register is used to
switch the allocation of registers.
[Registers allocated when the RPAGE bit is set to 0 (window 0 selected)]
• CAN receive rule entry registers: GAFLIDLj, GAFLIDHj, GAFLMLj, GAFLMHj, GAFLPLj, GAFLPHj
• CAN RAM test registers: RPGACCr
[Registers allocated when the RPAGE bit is set to 1 (window 1 selected)]
• CAN receive buffer registers: RMIDLn, RMIDHn, RMTSn, RMPTRn, RMDF0n to RMDF3n
• CAN receive FIFO access registers: RFIDLm, RFIDHm, RFTSm, RFPTRm, RFDF0m to RFDF3m
• CANi transmit/receive FIFO access registers: CFIDLk, CFIDHk, CFTSk, CFPTRk, CFDF0k to CFDF3k
• CANi transmit buffer registers: TMIDLp, TMIDHp, TMPTRp, TMDF0p to TMDF3p
• CANi transmit history buffer access register: THLACCi
Figure 18-15. RAM Window
0 1
RAM window select bit
Window 0 Window 1
CAN receive rule
entry registers
CAN RAM test registers
CAN receive buffer
registers
CAN receive FIFO
access registers
CANi transmit/receive
FIFO access registers
CANi transmit buffer
registers
CANi transmit history
buffer access register
Internal bus
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