Renesas RL78/F13 - CAN Receive Rule Entry Register Jcl (Gaflplj) (J = 0 to 15)

RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1313
Dec 10, 2015
18.3.22 CAN Receive Rule Entry Register jCL (GAFLPLj) (j = 0 to 15)
Address GAFLPL0L: F03A8H, GAFLPL0H: F03A9H GAFLPL1L: F03B4H, GAFLPL1H: F03B5H
GAFLPL2L: F03C0H, GAFLPL2H: F03C1H GAFLPL3L: F03CCH, GAFLPL3H: F03CDH
GAFLPL4L: F03D8H, GAFLPL4H: F03D9H GAFLPL5L: F03E4H, GAFLPL5H: F03E5H
GAFLPL6L: F03F0H, GAFLPL6H: F03F1H GAFLPL7L: F03FCH, GAFLPL7H: F03FDH
GAFLPL8L: F0408H, GAFLPL8H: F0409H GAFLPL9L: F0414H, GAFLPL9H: F0415H
GAFLPL10L: F0420H, GAFLPL10H: F0421H GAFLPL11L: F042CH, GAFLPL11H: F042DH
GAFLPL12L: F0438H, GAFLPL12H: F0439H GAFLPL13L: F0444H, GAFLPL13H: F0445H
GAFLPL14L: F0450H, GAFLPL14H: F0451H GAFLPL15L: F045CH, GAFLPL15H: F045DH
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
GAFL
RMV
GAFLRMDP[6:0] — — — GAFL
FDP4
— — GAFL
FDP1
GAFL
FDP0
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 GAFLRMV Receive Buffer Enable 0: No receive buffer is used.
1: A receive buffer is used.
R/W
14 to 8 GAFLRMDP
[6:0]
Receive Buffer Number Select Set the receive buffer number to store receive
messages.
R/W
7 to 5 — Reserved These bits are always read as 0. The write value should
always be 0.
R
4 GAFLFDP4 CAN0 Transmit/Receive FIFO Buffer
Select 0
0: Not select a CAN0 transmit/receive FIFO buffer 0
1: Select a CAN0 transmit/receive FIFO buffer 0
R/W
3, 2 — Reserved These bits are always read as 0. The write value should
always be 0.
R
1 GAFLFDP1 Receive FIFO Buffer Select 1 0: Not select a receive FIFO buffer 1
1: Select a receive FIFO buffer 1
R/W
0 GAFLFDP0 Receive FIFO Buffer Select 0 0: Not select a receive FIFO buffer 0
1: Select a receive FIFO buffer 0
R/W
Modify the GAFLPLj register only when the RPAGE bit in the GRWCR register is set to 0 in global reset mode.
• GAFLRMV Bit
When this bit is set to 1, receive messages that have passed through the filter are stored in the receive buffer
selected by the GAFLRMDP[6:0] bits.
• GAFLRMDP[6:0] Bits
These bits are used to select the number of the receive buffer that stores receive messages that have passed
through the filter when the GAFLRMV bit is set to 1. Set these bits to a value smaller than the value set by the
NRXMB[4:0] bits in the RMNB register.
• GAFLFDP4, GAFLFDP1, and GAFLFDP0 Bits
These bits are used to specify FIFO buffers that store receive messages that have passed through the filter. Up
to two FIFO buffers are selectable. However, when the GAFLRMV bit in the GAFLPLj register is set to 1 (a
receive buffer is used), up to one FIFO buffer is selectable. Only receive FIFO buffers and the transmit/receive
FIFO buffer for which the CFM[1:0] bits in the CFCCHk register are set to B'00 (receive mode) are selectable.