RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1312
Dec 10, 2015
18.3.21 CAN Receive Rule Entry Register jBH (GAFLMHj) (j = 0 to 15)
Address GAFLMH0L: F03A6H, GAFLMH0H: F03A7H GAFLMH1L: F03B2H, GAFLMH1H: F03B3H
GAFLMH2L: F03BEH, GAFLMH2H: F03BFH GAFLMH3L: F03CAH, GAFLMH3H: F03CBH
GAFLMH4L: F03D6H, GAFLMH4H: F03D7H GAFLMH5L: F03E2H, GAFLMH5H: F03E3H
GAFLMH6L: F03EEH, GAFLMH6H: F03EFH GAFLMH7L: F03FAH, GAFLMH7H: F03FBH
GAFLMH8L: F0406H, GAFLMH8H: F0407H GAFLMH9L: F0412H, GAFLMH9H: F0413H
GAFLMH10L: F041EH, GAFLMH10H: F041FH GAFLMH11L: F042AH, GAFLMH11H: F042BH
GAFLMH12L: F0436H, GAFLMH12H: F0437H GAFLMH13L: F0442H, GAFLMH13H: F0443H
GAFLMH14L: F044EH, GAFLMH14H: F044FH GAFLMH15L: F045AH, GAFLMH15H: F045BH
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
GAFL
IDEM
GAFL
RTRM
— GAFLIDM[28:16]
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 GAFLIDEM IDE Mask 0: The IDE bit is not compared.
1: The IDE bit is compared.
R/W
14 GAFLRTRM RTR Mask 0: The RTR bit is not compared.
1: The RTR bit is compared
R/W
13 — Reserved This bit is always read as 0. The write value should
always be 0.
R
12 to 0 GAFLIDM
[28:16]
ID Mask H 0: The corresponding ID bit is not compared.
1: The corresponding ID bit is compared.
R/W
Modify the GAFLMHj register only when the RPAGE bit in the GRWCR register is set to 0 in global reset mode.
• GAFLIDEM Bit
When this bit is set to 1, filter processing is performed only for messages of the ID format specified by the
GAFLIDE bit in the GAFLIDHj register.
When this bit is set to 0, it is regarded that all received messages have matched the specified ID format. To set
the GAFLIDEM bit to 0, set the GAFLIDM[28:16] bits in the GAFLMHj register and the GAFLIDM[15:0] bits in
the GAFLMLj register to all 0 at the same time.
• GAFLRTRM Bit
This bit is used to mask the RTR bit of the receive rule.
• GAFLIDM[28:16] Bits
These bits are used to mask the corresponding ID bit of the receive rule.
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