RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 817
Dec 10, 2015
15.3.10 Serial channel enable status register m (SEm)
The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped.
When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1. When
1 is written a bit of serial channel stop register m (STm), the corresponding bit is cleared to 0.
Channel n that is enabled to operate cannot rewrite by software the value of the CKOmn bit (serial clock output of
channel n) of serial output register m (SOm) to be described below, and a value reflected by a communication
operation is output from the serial clock pin.
Channel n that stops operation can set the value of the CKOmn bit of the SOm register by software and output its
value from the serial clock pin. In this way, any waveform, such as that of a start condition/stop condition, can be
created by software.
Read the SEm register by a 16-bit memory manipulation instruction.
Read the lower 8 bits of the SEm register with a 1-bit or 8-bit memory manipulation instruction with SFmL.
Reset signal generation clears the SEm register to 0000H.
Figure 15-13. Format of Serial Channel Enable Status Register m (SEm)
Address: F0110H, F0111H (SE0) After reset: 0000H R
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SE01 SE00
Address: F0150H, F0151H (SE1) After reset: 0000H R
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SE1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SE11 SE10
SEm
n
Indication of operation enable/stop status of channel n
0 Operation stops
Note
1 Operation is enabled.
Note The control register, shift register value, serial clock I/O pin, serial data output pin, and error flags (FEFmn:
framing error flag, PEFmn: parity error flag, OVFmn: over error flag)) are stopped with the state retained. Bits
6 and 5 (TSFmn and BFFmn) in the SSRmn register are cleared.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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