RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 570
Dec 10, 2015
8.2.1 Peripheral enable register 1 (PER1)
The PER1 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the
hardware that is not used is also stopped so as to decrease the power consumption and noise.
To use timer RD, be sure to set bit 4 (TRD0EN) to 1.
Set the PER1 register by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 8-2. Format of Peripheral Enable Register 1 (PER1)
Address: F02C0H After reset: 00H R/W
Symbol <7> 6 <5> <4> <3> 2 1 <0>
PER1 DACEN
Note
0 CMPEN
Note
TRD0EN DTCEN 0 0 TRJ0EN
TRD0EN Control of timer RD input clock supply
0
Stops input clock supply.
ï‚· SFR used by timer RD cannot be written.
ï‚· Timer RD is in the reset status.
1
Enables input clock supply.
ï‚· SFR used by timer RD can be read and written.
Note Only for RL78/F14.
Cautions 1. When setting timer RD, be sure to set the TRD0EN bit to 1 first. If TRD0EN = 0,
writing to a control register of timer RD is ignored, and all read values are default
values (except for port mode registers 1, 3, and 12 (PM1, PM3, and PM12) and port
registers 1, 3, and 12 (P1, P3, and P12).
2. Be sure to clear the following bits to 0.
RL78/F13: bits 1, 2, and 5 to 7
RL78/F14: bits 1, 2, and 6
3. When selecting f
IF (64 MHz or 48 MHz) as the count source, set fCLK to fIH. When
selecting f
PLL (over 32 MHz) as the count source, set fCLK to fPLL. When selecting fSUB
or f
IL as the count source to access the timer RD-related registers, set fCLK to fSUB or
f
IL, respectively.
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