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Renesas RL78/F13

Renesas RL78/F13
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RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 793
Dec 10, 2015
15.1 Functions of Serial Array Unit
Each serial interface supported by the RL78/F13 and RL78/F14 has the following features.
15.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11)
Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel.
3-wire serial communication is clocked communication performed by using three communication lines: one for the serial
clock (SCK), one for transmitting serial data (SO), one for receiving serial data (SI).
For details about the settings, see 15.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11) Communication.
[Data transmission/reception]
Data length of 7 to 16 bits
Phase control of transmit/receive data
MSB/LSB first selectable
Level setting of transmit/receive data
[Clock control]
Master/slave selection
Phase control of I/O clock
Setting of transfer period by prescaler and internal counter of each channel
Maximum transfer rate
During master communication: Max. f
MCK/4
Note
During slave communication: Max. f
MCK/6
Note
[Interrupt function]
Transfer end interrupt/buffer empty interrupt
[Error detection flag]
Overrun error
CSI00, CSI01, CSI10, and CSI11 support the SPI function.
[Extended function]
Slave select function of the SPI function
Note Use the clocks within a range satisfying the SCK cycle time (t
KCY) characteristics (see CHAPTER 34 to
CHAPTER 36 ELECTRICAL SPECIFICATIONS).

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