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Renesas RL78/F13 - CAN Receive FIFO Access Register Mcl (Rfdf0 M) (M = 0, 1)

Renesas RL78/F13
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RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1334
Dec 10, 2015
18.3.41 CAN Receive FIFO Access Register mCL (RFDF0m) (m = 0, 1)
Address RFDF00L: F05A8H, RFDF00H: F05A9H
RFDF01L: F05B8H, RFDF01H: F05B9H
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
RFDB1[7:0] RFDB0[7:0]
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 to 8 RFDB1[7:0] Receive FIFO Buffer Data Byte 1 Data in the message stored in the receive FIFO buffer
can be read.
R
7 to 0 RFDB0[7:0] Receive FIFO Buffer Data Byte 0 R
When the RFDLC[3:0] value in the RFPTRm register is smaller than B'1000, data bytes for which no data is set are
read as H'00.
This register can be read when the RPAGE bit in the GRWCR register is 1.

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