RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 823
Dec 10, 2015
15.3.16 Noise filter enable register 0 (NFEN0)
The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input
pin to each channel.
Disable the noise filter of the pin used for CSI or simplified I
2
C communication, by clearing the corresponding bit of
this register to 0.
Enable the noise filter of the pin used for UART communication, by setting the corresponding bit of this register to
1.
When the noise filter is enabled, CPU/peripheral hardware clock (f
CLK) is synchronized with 2-clock match detection.
When the noise filter is OFF, only synchronization is performed with the CPU/peripheral hardware clock (f
MCK)
Note
.
Set the NFEN0 register by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the NFEN0 register to 00H.
Note For details, see 6.5.1 (2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1) and
6.5.2 Start timing of counter.
Figure 15-19. Format of Noise Filter Enable Register 0 (NFEN0)
Address: F0070H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
NFEN0 0 0 0 0 0
SNFEN10
Note
0 SNFEN00
SNFEN10 Use of noise filter of RXD1 pin
0 Noise filter OFF
1 Noise filter ON
Set the SNFEN10 bit to 1 to use the RXD1 pin.
Clear the SNFEN10 bit to 0 to use the other than RxD1 pin.
SNFEN00 Use of noise filter of RXD0 pin
0 Noise filter OFF
1 Noise filter ON
Set the SNFEN00 bit to 1 to use the RXD0 pin.
Clear the SNFEN00 bit to 0 to use the other than RxD0 pin.
Note Not provided in the Group A products.
Caution Be sure to clear the following bits to 0.
• Bits 7 to 1 in the Group A products
• Bits 7 to 3 and 1 in the products other than above
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