RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1154
Dec 10, 2015
LNRR bit (no-response request bit)
Set the LNRR bit to 1 when neither response transmission nor reception is started after the header is received and the
received ID is checked.
Once set, this bit is automatically cleared to 0 upon detection of the new sync field or transition to LIN reset mode.
Only 1 can be written to this bit; 0 cannot be written.
To write 1 to this bit, write 04H to the LTRCn register by using an 8-bit data transfer instruction.
Do not set this bit and the RTS bit to 1 simultaneously.
Writing a value to this bit is disabled when the OMM0 bit in the LMSTn register is 0 (LIN reset mode).
Writing a value to this bit is disabled when the FTS bit is 0 (header reception or wake-up transmission/reception is stopped).
When a 9-byte or longer response is to be transmitted or received, do not use this bit other than on completion of header
reception (do not use this bit on completion of the second and subsequent data groups).
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