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Renesas RL78/F13 - Page 1192

Renesas RL78/F13
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RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1160
Dec 10, 2015
(20) LIN/UART Data Field Configuration Register (LDFCn)
Address: F06D4H
7 6 5 4 3 2 1 0
LSS — LCS RCDS RFDL[3:0]
Value after reset:
0 0 0 0 0 0 0 0
Bit Symbol Bit Name Function R/W
3 to 0 RFDL[3:0] Response Field Length Select
b3 b0
0 0 0 0: 0 byte (+ checksum)
0 0 0 1: 1 byte (+ checksum)
0 0 1 0: 2 bytes (+ checksum)
:
0 1 1 1: 7 bytes (+ checksum)
1 0 0 0: 8 bytes (+ checksum)
Settings other than the above are prohibited.
R/W
4 RCDS Response Field Communication Direction
Select
0: Reception
1: Transmission
R/W
5 LCS Checksum Select 0: Classic checksum mode
1: Enhanced checksum mode
R/W
6 Reserved This bit is always read as 0. The write value should
always be 0.
R/W
7 LSS Transmission/Reception Continuation
Select
0: The data group to be transmitted/received next is the
last one.
1: The data group to be transmitted/received next is not
the last one.
(Data transmission/reception is continued without
waiting for the next header reception.)
R/W
RFDL[3:0] bits (response field length select bits)
The RFDL bits set the length of the response field data.
The data length can be 0 to 8 bytes excluding the checksum size.
Set these bits when the RTS bit is 0 (response transmission/reception stopped).
When response data of 9 bytes or more is to be transmitted and received, only the last data group (the LSS bit is 0) includes
the checksum, and no other groups (the LSS bit is 1) include the checksum.
RCDS bit (response field communication direction select bit)
The RCDS bit sets the direction of the response field/wake-up signal communication.
With 0 set, reception is performed in the response field. In LIN wake-up mode, wake-up reception is performed (low width
of the input signal is counted).
With 1 set, transmission is performed in the response field. In LIN wake-up mode, wake-up transmission is performed.
When the module is in the LIN operating mode, set this bit while the RTS bit in the LTRCn register is 0 (response
transmission/reception stopped). When the module is in the LIN wakeup mode, set this bit while the FTS bit in the LTRCn
register is 0 (header reception or wake-up transmission/reception stopped).
When response data of 9 bytes or more is to be transmitted or received, do not change the RCDS bit setting after the first
data group through the last data group.
<R>

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