RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1296
Dec 10, 2015
See the CAN specifications (ISO11898-1) if you want to check error occurrence conditions. To clear each flag of this
register, write 0 by the program. These flags cannot be set to 1 by the program. If any of these flags is set to 1 at the
timing when the program writes 0 to the flag, the flag is set to 1. Each flag is cleared to 0 in channel reset mode.
With respect to bits 14 to 8 in the CiERFLL register, if an error is detected with all flags of bits 14 to 8 set to 0 when the
ERRD bit in the CiCTRH register is set to 0 (only the first error information is displayed), the corresponding flag is set to 1.
• ADERR Flag
This flag is set to 1 when a form error has been detected in the ACK delimiter during transmission.
• B0ERR Flag
This flag is set to 1 when a recessive bit has been detected though a dominant bit was transmitted.
• B1ERR Flag
This flag is set to 1 when a dominant bit has been detected though a recessive bit was transmitted.
• CERR Flag
This flag is set to 1 when a CRC error has been detected.
• AERR Flag
This flag is set to 1 when an ACK error has been detected.
• FERR Flag
This flag is set to 1 when a form error has been detected.
• SERR Flag
This flag is set to 1 when a stuff error has been detected.
• ALF Flag
This flag is set to 1 when an arbitration lost has been detected.
• BLF Flag
This flag is set to 1 when 32 consecutive dominant bits have been detected on the CAN bus in channel
communication mode. After that, detection of the bus lock becomes possible again if either of the following
conditions is met.
• A recessive bit is detected after the BLF bit has been modified from 1 to 0.
• The CAN module transitions to channel reset mode and returns to channel communication mode after the BLF
bit has been modified from 1 to 0.
• OVLF Flag
This flag is set to 1 when the overload frame transmit condition has been detected when performing reception or
transmission.
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