RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 119
Dec 10, 2015
The PMC register is described below.
ï‚· Processor mode control register (PMC)
This register sets the flash memory space for mirroring to area from F0000H to FFFFFH.
The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 3-18. Format of Configuration of Processor Mode Control Register (PMC)
Address: FFFFEH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 <0>
PMC 0 0 0 0 0 0 0 MAA
MAA Selection of flash memory space for mirroring to area from F0000H to FFFFFH
0 00000H to 0FFFFH is mirrored to F0000H to FFFFFH
1 10000H to 1FFFFH is mirrored to F0000H to FFFFFH
Note
Note This setting is prohibited in products with 64 KB or less flash memory
Cautions 1. In products with 64 KB or less flash memory, be sure to clear bit 0 (MAA) of this register to 0 (default
value).
2. Set the PMC register only once during the initial settings prior to operating the data transfer
controller (DTC). Rewriting the PMC register other than during the initial settings is prohibited.
3. After setting the PMC register, wait for at least one instruction and access the mirror area.
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