Renesas RL78/F13 - Page 176

RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 144
Dec 10, 2015
Figure 3-40. Configuration of General-Purpose Registers
(a) Function name
(b) Absolute name
Register bank 0
Register bank 1
Register bank 2
Register bank 3
FFEFFH
FFEF8H
FFEE0H
HL
DE
BC
AX
H
15 0 7 0
L
D
E
B
C
A
X
16-bit processing
8-bit processing
FFEF0H
FFEE8H
Register bank 0
Register bank 1
Register bank 2
Register bank 3
FFEFFH
FFEF8H
FFEE0H
RP3
RP2
RP1
RP0
R7
15 0 7 0
R6
R5
R4
R3
R2
R1
R0
16-bit processing
8-bit processing
FFEF0H
FFEE8H