Renesas RL78/F13

RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 169
Dec 10, 2015
Table 3-6. Extended SFR (2nd SFR) List (18/32)
Address Special Function Register (2nd SFR) Name Symbol R/W Manipulable Bit Range After
reset
1-bit 8-bit 16-bit
F041AH CAN receive rule entry register 10AH
Note 1
GAFLIDH10L GAFLIDH10 R/W – √ √ 0000H
F041BH GAFLIDH10H – √
F041AH CAN receive buffer register 7CH
Note 2
RMDF17L RMDF17 R – √ √ 0000H
F041BH RMDF17H – √
F041CH CAN receive rule entry register 10BL
Note 1
GAFLML10L GAFLML10 R/W – √ √ 0000H
F041DH GAFLML10H – √
F041CH CAN receive buffer register 7DL
Note 2
RMDF27L RMDF27 R – √ √ 0000H
F041DH RMDF27H – √
F041EH CAN receive rule entry register 10BH
Note 1
GAFLMH10L GAFLMH10 R/W – √ √ 0000H
F041FH GAFLMH10H – √
F041EH CAN receive buffer register 7DH
Note 2
RMDF37L RMDF37 R – √ √ 0000H
F041FH RMDF37H – √
F0420H CAN receive rule entry register 10CL
Note 1
GAFLPL10L GAFLPL10 R/W – √ √ 0000H
F0421H GAFLPL10H – √
F0420H CAN receive buffer register 8AL
Note 2
RMIDL8L RMIDL8 R – √ √ 0000H
F0421H RMIDL8H – √
F0422H CAN receive rule entry register 10CH
Note 1
GAFLPH10L GAFLPH10 R/W – √ √ 0000H
F0423H GAFLPH10H – √
F0422H CAN receive buffer register 8AH
Note 2
RMIDH8L RMIDH8 R – √ √ 0000H
F0423H RMIDH8H – √
F0424H CAN receive rule entry register 11AL
Note 1
GAFLIDL11L GAFLIDL11 R/W – √ √ 0000H
F0425H GAFLIDL11H – √
F0424H CAN receive buffer register 8BL
Note 2
RMTS8L RMTS8 R – √ √ 0000H
F0425H RMTS8H – √
F0426H CAN receive rule entry register 11AH
Note 1
GAFLIDH11L GAFLIDH11 R/W – √ √ 0000H
F0427H GAFLIDH11H – √
F0426H CAN receive buffer register 8BH
Note 2
RMPTR8L RMPTR8 R – √ √ 0000H
F0427H RMPTR8H – √
F0428H CAN receive rule entry register 11BL
Note 1
GAFLML11L GAFLML11 R/W – √ √ 0000H
F0429H GAFLML11H – √
F0428H CAN receive buffer register 8CL
Note 2
RMDF08L RMDF08 R – √ √ 0000H
F0429H RMDF08H – √
F042AH CAN receive rule entry register 11BH
Note 1
GAFLMH11L GAFLMH11 R/W – √ √ 0000H
F042BH GAFLMH11H – √
F042AH CAN receive buffer register 8CH
Note 2
RMDF18L RMDF18 R – √ √ 0000H
F042BH RMDF18H – √
F042CH CAN receive rule entry register 11CL
Note 1
GAFLPL11L GAFLPL11 R/W – √ √ 0000H
F042DH GAFLPL11H – √
F042CH CAN receive buffer register 8DL
Note 2
RMDF28L RMDF28 R – √ √ 0000H
F042DH RMDF28H – √
F042EH CAN receive rule entry register 11CH
Note 1
GAFLPH11L GAFLPH11 R/W – √ √ 0000H
F042FH GAFLPH11H – √
Notes 1. These registers are allocated to the RAM window 0 for the CAN module (receive rule and CAN RAM test register).
When setting these registers, set the RPAGE bit in the GRWCR register to 0.
2. These registers are allocated to the RAM window 1 for the CAN module (receive buffer, receive FIFO buffer,
transmit/receive FIFO buffer, transmit buffer, and transmit history data). When setting these registers, set the
RPAGE bit in the GRWCR register to 1.