Renesas RL78/F13

RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 177
Dec 10, 2015
Table 3-6. Extended SFR (2nd SFR) List (26/32)
Address Special Function Register (2nd SFR) Name Symbol R/W Manipulable Bit Range After
reset
1-bit 8-bit 16-bit
F05E8H CAN0 transmit/receive FIFO access register
0CL
Note 2
CFDF00L CFDF00 R/W – √ √ 0000H
F05E9H CFDF00H – √
F05EAH CAN RAM test register 53
Note 1
RPGACC53L RPGACC53 R/W – √ √ 0000H
F05EBH RPGACC53H – √
F05EAH CAN0 transmit/receive FIFO access register
0CH
Note 2
CFDF10L CFDF10 R/W – √ √ 0000H
F05EBH CFDF10H – √
F05ECH CAN RAM test register 54
Note 1
RPGACC54L RPGACC54 R/W – √ √ 0000H
F05EDH RPGACC54H – √
F05ECH CAN0 transmit/receive FIFO access register
0DL
Note 2
CFDF20L CFDF20 R/W – √ √ 0000H
F05EDH CFDF20H – √
F05EEH CAN RAM test register 55
Note 1
RPGACC55L RPGACC55 R/W – √ √ 0000H
F05EFH RPGACC55H – √
F05EEH CAN0 transmit/receive FIFO access register
0DH
Note 2
CFDF30L CFDF30 R/W – √ √ 0000H
F05EFH CFDF30H – √
F05F0H CAN RAM test register 56
Note 1
RPGACC56L RPGACC56 R/W – √ √ 0000H
F05F1H RPGACC56H – √
F05F2H CAN RAM test register 57
Note 1
RPGACC57L RPGACC57 R/W – √ √ 0000H
F05F3H RPGACC57H – √
F05F4H CAN RAM test register 58
Note 1
RPGACC58L RPGACC58 R/W – √ √ 0000H
F05F5H RPGACC58H – √
F05F6H CAN RAM test register 59
Note 1
RPGACC59L RPGACC59 R/W – √ √ 0000H
F05F7H RPGACC59H – √
F05F8H CAN RAM test register 60
Note 1
RPGACC60L RPGACC60 R/W – √ √ 0000H
F05F9H RPGACC60H – √
F05FAH CAN RAM test register 61
Note 1
RPGACC61L RPGACC61 R/W – √ √ 0000H
F05FBH RPGACC61H – √
F05FCH CAN RAM test register 62
Note 1
RPGACC62L RPGACC62 R/W – √ √ 0000H
F05FDH RPGACC62H – √
F05FEH CAN RAM test register 63
Note 1
RPGACC63L RPGACC63 R/W – √ √ 0000H
F05FFH RPGACC63H – √
F0600H CAN RAM test register 64
Note 1
RPGACC64L RPGACC64 R/W – √ √ 0000H
F0601H RPGACC64H – √
F0600H CAN0 transmit buffer register 0AL
Note 2
TMIDL0L TMIDL0 R/W – √ √ 0000H
F0601H TMIDL0H – √
F0602H CAN RAM test register 65
Note 1
RPGACC65L RPGACC65 R/W – √ √ 0000H
F0603H RPGACC65H – √
F0602H CAN0 transmit buffer register 0AH
Note 2
TMIDH0L TMIDH0 R/W – √ √ 0000H
F0603H TMIDH0H – √
F0604H CAN RAM test register 66
Note 1
RPGACC66L RPGACC66 R/W – √ √ 0000H
F0605H RPGACC66H – √
F0606H CAN RAM test register 67
Note 1
RPGACC67L RPGACC67 R/W – √ √ 0000H
F0607H RPGACC67H – √
Notes 1. These registers are allocated to the RAM window 0 for the CAN module (receive rule and CAN RAM test register).
When setting these registers, set the RPAGE bit in the GRWCR register to 0.
2. These registers are allocated to the RAM window 1 for the CAN module (receive buffer, receive FIFO buffer,
transmit/receive FIFO buffer, transmit buffer, and transmit history data). When setting these registers, set the
RPAGE bit in the GRWCR register to 1.