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RM0440 Rev 4 2001/2126

RM0440 FD controller area network (FDCAN)

2008

44.4.31 FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO)

Address offset: 0x00D4

Reset value: 0x0000 0000

44.4.32 FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF)

Address offset: 0x00D8

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TO[2:0]

rrr

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 TO[2:0]: Transmission occurred.

Each Tx buffer has its own TO bit. The bits are set when the corresponding TXBRP bit is

cleared after a successful transmission. The bits are reset when a new transmission is

requested by writing a 1 to the corresponding bit of register TXBAR.

0: No transmission occurred

1: Transmission occurred

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CF[2:0]

rrr

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 CF[2:0]: Cancellation finished

Each Tx buffer has its own CF bit. The bits are set when the corresponding TXBRP bit is

cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit

was not set at the point of cancellation, CF is set immediately. The bits are reset when a new

transmission is requested by writing a 1 to the corresponding bit of register TXBAR.

0: No transmit buffer cancellation

1: Transmit buffer cancellation finished

ST STM32G431 User Manual

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