Contents RM0440
32/2126 RM0440 Rev 4
30.7.17 TIM15 timer deadtime register 2 (TIM15_DTR2) . . . . . . . . . . . . . . . . 1412
30.7.18 TIM15 input selection register (TIM15_TISEL) . . . . . . . . . . . . . . . . . 1413
30.7.19 TIM15 alternate function register 1 (TIM15_AF1) . . . . . . . . . . . . . . . 1414
30.7.20 TIM15 alternate function register 2 (TIM15_AF2) . . . . . . . . . . . . . . . 1416
30.7.21 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . 1417
30.7.22 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . 1417
30.7.23 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418
30.8 TIM16/TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421
30.8.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . . . . . . . . . . . . 1421
30.8.2 TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . . . . . . . . . . . . 1422
30.8.3 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . 1423
30.8.4 TIMx status register (TIMx_SR)(x = 16 to 17) . . . . . . . . . . . . . . . . . . 1424
30.8.5 TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . . . . . 1425
30.8.6 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1426
30.8.7 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1427
30.8.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . 1429
30.8.9 TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . 1432
30.8.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . 1432
30.8.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . . . . . . . . . 1433
30.8.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . . . . . 1433
30.8.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . . 1434
30.8.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . 1435
30.8.15 TIMx option register 1 (TIMx_OR1)(x = 16 to 17) . . . . . . . . . . . . . . . 1438
30.8.16 TIMx timer deadtime register 2 (TIMx_DTR2)(x = 16 to 17) . . . . . . . 1438
30.8.17 TIMx input selection register (TIMx_TISEL)(x = 16 to 17) . . . . . . . . . 1439
30.8.18 TIMx alternate function register 1 (TIMx_AF1)(x = 16 to 17) . . . . . . . 1439
30.8.19 TIMx alternate function register 2 (TIMx_AF2)(x = 16 to 17) . . . . . . . 1442
30.8.20 TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . . . . . . . . . 1442
30.8.21 TIM16/TIM17 DMA address for full transfer
(TIMx_DMAR)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1443
30.8.22 TIM16/TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1444
31 Basic timers (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446
31.1 TIM6/TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446
31.2 TIM6/TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446
31.3 TIM6/TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447
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