CLA Memory Configuration Register
Cla1Regs.MMEMCFG
PROGE
07
reserved
RAM1E RAM0E
45 3 - 1
reserved
RAM2E
15 - 11
reserved
RAM1CPUE RAM0CPUE
910
RAM2CPUE
6
8
CLA Data RAM2 / RAM1 / RAM0 Enable
0 = mapped to CPU program and data space
1 = mapped to CLA data space
CLA Program Space Enable
0 = mapped to CPU program and data space
1 = mapped to CLA program space
CLA Data RAM2 / RAM1 / RAM0 CPU Access Enable
0 = mapped as RAM2E / RAM1E / RAM0
1 = CPU access to RAM while mapped to CLA data space
CLA Peripheral Interrupt Source
Select 1 Register
Cla1Regs.MPISRCSEL1
PERINT8SEL
31 - 28 19 - 16
PERINT7SEL PERINT6SEL PERINT5SEL
27 - 24 23 - 20
0000 = DefaultNote: select ‘no source’ if task is generated by software
Upper Register:
Task 8 Peripheral
Interrupt Input
0000 = ADCINT8
0010 = CPU Timer 0
0100 = eQEP1
0101 = eQEP2
1000 = eCAP1
1001 = eCAP2
1010 = eCAP3
other = no source
Task 7 Peripheral
Interrupt Input
0000 = ADCINT7
0010 = ePWM7
0100 = eQEP1
0101 = eQEP2
1000 = eCAP1
1001 = eCAP2
1010 = eCAP3
other = no source
Task 6 Peripheral
Interrupt Input
0000 = ADCINT6
0010 = ePWM6
0100 = eQEP1
0101 = eQEP2
1000 = eCAP1
1001 = eCAP2
1010 = eCAP3
other = no source
Task 5 Peripheral
Interrupt Input
0000 = ADCINT5
0010 = ePWM5
0100 = eQEP1
0101 = eQEP2
1000 = eCAP1
1001 = eCAP2
1010 = eCAP3
other = no source