Oscillator/PLL Clock Module
5 - 4 C2000 Microcontroller Workshop - System Initialization
F2806x PLL and LOSPCP
(lab file: SysCtrl.c)
DIV CLKIN
0 0 0 0 0 OSCCLK / n * (PLL bypass)
0 0 0 0 1 OSCCLK x 1 / n
0 0 0 1 0 OSCCLK x 2 / n
0 0 0 1 1 OSCCLK x 3 / n
0 0 1 0 0 OSCCLK x 4 / n
0 0 1 0 1 OSCCLK x 5 / n
0 0 1 1 0 OSCCLK x 6 / n
0 0 1 1 1 OSCCLK x 7 / n
0 1 0 0 0 OSCCLK x 8 / n
0 1 0 0 1 OSCCLK x 9 / n
0 1 0 1 0 OSCCLK x 10 / n
0 1 0 1 1 OSCCLK x 11 / n
0 1 1 0 0 OSCCLK x 12 / n
0 1 1 0 1 OSCCLK x 13 / n
0 1 1 1 0 OSCCLK x 14 / n
0 1 1 1 1 OSCCLK x 15 / n
1 0 0 0 0 OSCCLK x 16 / n
1 0 0 0 1 OSCCLK x 17 / n
1 0 0 1 0 OSCCLK x 18 / n
1 x x 1 1 reserved
Input Clock Fail Detect Circuitry
PLL will issue a “limp mode” clock (1-4 MHz) if input
clock is removed after PLL has locked.
An internal device reset will also be issued (XRSn
pin not driven).
DIVSEL n
0x /4 *
10 /2
11 /1
* default
PLL
VCOCLK
OSCCLK
C28x
Core
CLKIN
SYSCLKOUT
LOSPCP
(PLL bypass)
LSPCLK
MUX
1/n
SysCtrlRegs.PLLCR.bit.DIV
SysCtrlRegs.PLLSTS.bit.DIVSEL
SysCtrlRegs.LOSPCP.bit.LSPCLK
LSPCLK Peripheral Clk Freq
0 0 0 SYSCLKOUT / 1
0 0 1 SYSCLKOUT / 2
0 1 0 SYSCLKOUT / 4 *
0 1 1 SYSCLKOUT / 6
1 0 0 SYSCLKOUT / 8
1 0 1 SYSCLKOUT / 10
1 1 0 SYSCLKOUT / 12
1 1 1 SYSCLKOUT / 14
LSBs in reg. – others reserved
A clock source can be fed directly into the core or multiplied using the PLL. The PLL gives us
the capability to use the internal 10 MHz oscillator multiplied by 18/2, and run the device at the
full 90 MHz clock frequency. If the input clock is removed after the PLL is locked, the input
clock failed detect circuitry will issue a limp mode clock of 1 to 4 MHz. Additionally, an internal
device reset will be issued. The low-speed peripheral clock prescaler is used to clock some of the
communication peripherals.
The PLL has a 4-bit ratio control to select different CPU clock rates. In addition to the on-chip
oscillators, two external modes of operation are supported – crystal operation, and external clock
source operation. Crystal operation allows the use of an external crystal/resonator to provide the
time base to the device. External clock source operation allows the internal (crystal) oscillator to
be bypassed, and the device clocks are generated from an external clock source input on the
XCLKIN pin. The C28x core provides a SYSCLKOUT clock signal. This signal is prescaled to
provide a clock source for some of the on-chip communication peripherals through the low-speed
peripheral clock prescaler. Other peripherals are clocked by SYSCLKOUT and use their own
clock prescalers for operation.