Oscillator/PLL Clock Module
5 - 6 C2000 Microcontroller Workshop - System Initialization
Peripheral Clock Control Registers
(lab file: SysCtrl.c)
Module Enable Clock Bit 0 = disable
(default)
1 = enable
15 14 13 11 10 9 812
7 6 5 4 3 2 1 0
SysCtrlRegs.
PCLKCR0
ECANA
ENCLK
SCIA
ENCLK
SPIA
ENCLK
I2CA
ENCLK
ADC
ENCLK
TBCLK
SYNC
reserved
reserved
HRPWM
ENCLK
SPIB
ENCLK
reserved reserved
reserved
15 14 13 11 10 9 812
7 6 5 4 3 2 1 0
EQEP1
ENCLK
ECAP1
ENCLK
EPWM6
ENCLK
EPWM5
ENCLK
EPWM4
ENCLK
EPWM3
ENCLK
EPWM2
ENCLK
EPWM1
ENCLK
EPWM7
ENCLK
reserved reserved reserved
SysCtrlRegs.
PCLKCR1
reserved reserved reserved reserved reserved
15 14 13 11 10 9 812
7 6 5 4 3 2 1 0
SysCtrlRegs.
PCLKCR2
SCIB
ENCLK
MCBSPA
ENCLK
reserved
ECAP2
ENCLK
ECAP3
ENCLK
EQEP2
ENCLK
EPWM8
ENCLK
reserved reserved reserved reserved
HRCAP1
ENCLK
HRCAP2
ENCLK
HRCAP3
ENCLK
HRCAP4
ENCLK
reserved
reserved
reserved
15 14 13 11 10 9 812
CPUTIMER2
ENCLK
CPUTIMER1
ENCLK
CPUTIMER0
ENCLK
reserved
7 6 5 4 3 2 1 0
reserved reserved reserved reserved reserved
COMP1
ENCLK
COMP2
ENCLK
COMP3
ENCLK
CLA1
ENCLK
SysCtrlRegs.
PCLKCR3
DMA
ENCLK
USB0
ENCLK
reserved
The peripheral clock control register allows individual peripheral clock signals to be enabled or
disabled. If a peripheral is not being used, its clock signal could be disabled, thus reducing power
consumption.