360 Chapter7
General Troubleshooting
Block Diagram Description
The cal oscillator output has three forms (all −35 dBm):
• 10.7 MHz
• 9.9 to 11.5 MHz in 100 kHz steps
• Frequency sweeps from 20 kHz to 2 kHz centered at 10.7 MHz
(lasting 5 to 60 ms respectively)
The purpose of these signals is:
• Adjust gains, log amps, and video slopes and offsets
• Adjust 3 dB bandwidth and center frequencies of LC resolution BW
filters (30 kHz through 1 MHz).
• Adjust 3 dB bandwidth, symmetry, and gain of the crystal resolution
BW filters (300 Hz through 10 kHz).
• Adjust gain and gain-vs-frequency for digital resolution bandwidths
(1 Hz through 100 Hz).
A5 IF Assembly
The A5 IF assembly has four crystal filter poles, four LC filter poles,
and step gain amplifiers. The crystal filters provide resolution
bandwidths of 300 Hz to 10 kHz. The LC filters provide resolution
bandwidths of 30 kHz to 2 MHz. All filter stages are in series. PIN diode
switches bypass unwanted stages.
An automatic IF adjustment, in spectrum analyzer firmware, sets
center frequency and 3 dB bandwidth of all filter poles through varactor
and PIN diodes. The firmware also controls crystal-pole symmetry and
the step gain amplification.
ADC/Interface Section
The ADC/interface section is the link between the controller section and
the rest of the spectrum analyzer. It controls the RF, synthesizer, and IF
sections through address and data lines on the W2 control cable (analog
bus). Analog signals from these sections are monitored by the ADC
(analog to digital converter) circuit on the ADC/interface section.
The ADC/interface section includes the A3 interface assembly, A1A1
keyboard, and A1A2 RPG (front panel knob). The A3 assembly includes
log expand, video filter, peak detector, track-and-hold, real-time DACs,
RF gain DACs, +10 V reference, and ADC circuitry. The digital section
of the A3 assembly includes ADC ASM, sweep trigger, keyboard
interface, RPG interface, and analog bus interface circuitry.
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