538 Chapter11
Synthesizer Section
Unlocked Reference PLL (100 MHz VCXO)
8. If the 100 MHz oscillator is working, the reason for the unlocked
condition is either a problem in the 10 MHz reference or a fault in
the signal path around the loop.
Check 10 MHz
reference to
phase/frequency
detector (steps
9-14)
9. On the spectrum analyzer, press
AUX CTRL, REAR PANEL, and 10 MHz
INT.
10.Check the 10 MHz reference frequency-accuracy by connecting a
frequency counter to A15J301 and verify that the reference
frequency is 10 MHz ±40 Hz after a 5 minute warm-up period.
11.If a 10 MHz signal >1 V peak-to-peak is not present at A15J301,
refer to the “10 MHz Reference” in Chapter 12 .
12.Measure the signal at TP301 with an oscilloscope. Refer to function
block M of A15 RF schematic (sheet 2 of 4).
13.Measure the signal at U502 pin 11 with an oscilloscope. Refer to
function block X of A15 RF schematic (sheet 2 of 4). This signal
should be TTL levels at 10 MHz with a 60 percent duty cycle.
14.If TTL-level signals (approximately 10 MHz) are not present, check
signals backwards through the loop to find a fault in the signal path.
15.Measure the signals at the following test points with an active
probe/spectrum analyzer combination:
16.If an approximately 10 MHz TTL signal is present at U502 pin 11
with 60 percent duty cycle, and the RF portion of the phase-lock loop
is functioning, the fault probably lies in the phase/frequency detector
or the 100 MHz lock loop integrator.
Check
phase/frequency
detector (steps
17-22)
17.Monitor U504 pin 5 and U503 pin 9 with an oscilloscope. These are
the two outputs of the phase/frequency detector. Refer to function
block O of A15 RF schematic (sheet 2 of 4).
18.A locked loop will exhibit stable, narrow (approximately 20 ns wide),
and positive-going TTL pulses occurring at a 10 MHz rate at U504
pin 5 and U503 pin 9.
Junction of C570 and C571 100 MHz, +2.5 dBm ±2 dB
Junction of R715, R716, 100 MHz, −3 dBm ±2 dB
R567, and R568
U700 pin 3 100 MHz, +16.5 dBm ±2 dB
U700 pin 1 100 MHz, +8.5 dBm ±2 dB
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