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Astraada SRV-64 - Checking for Communication Frame Errors

Astraada SRV-64
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AS64 series AC servo drive Communication
-254-
Write MSB of data start address
03H
Write LSB of data start address
F2H
MSB of data count (in word)
00H
LSB of data count (in word)
02H
CRC CHK LSB
E0H
CRC CHK MSB
7FH
END
T1-T2-T3-T4 (3.5-byte transmission time)
8.2.5 Checking for communication frame errors
Checking for communication frame errors consists of bit checking (that is, parity checking) for bytes
and entire-data checking (that is, CRC or LRC) for frames.
8.2.5.1 Bit checking for bytes
You can select different methods or even no checking based on your requirements, which affects the
check bit setting of each byte.
Even parity: An even parity bit is added before data transmission, indicating the number of 1 in the
transmitted data is even or odd. If the number is even, the parity bit is 0. Otherwise, the parity bit is 1.
Odd parity: An odd parity bit is added before data transmission, indicating the number of 1 in the
transmitted data is even or odd. If the number is odd, the parity bit is 0. Otherwise, the parity bit is 1.
Example: The number 11001110 is to be transmitted: If even parity is used, the even parity bit is 1; if
odd parity is used, the odd parity bit is 0. During transmission, the even/odd parity bit is placed in the
parity check position after calculation.
8.2.5.2 Cyclical Redundancy Check (CRC)
An RTU frame includes the domain for checking for errors in the entire frame using the CRC method.
This CRC domain consists of two bytes, including 16-bit hexadecimals. It is added to the frame after
being calculated by the sender. The receiver recalculates the CRC in the received frame and compares
it with the value in the received CRC domain. If the CRC values are different, a transmission error
occurred.
Before CRC, 0xFFFF is stored to the register, and then a process is invoked to compare the successive
6 bytes or more with the values in the register. Only when the 8-bit data in each character is valid to
CRC, the start bit, stop bit, and parity bit are invalid.
During CRC generation, each 8-bit character has an independent exclusive or relationship with register
content. The comparison result moves towards the LSB direction, and 0 is padded to the MSB. Then
the LSB is extracted for detection. If the LSB is 1, the register and preset value have an independent
exclusive or relationship. If the LSB is not 0, there is no such a relationship. The processing is repeated
eight times. When the eighth bit of the current character is checked, the next each 8-bit character is
checked for an independent exclusive or relationship with register content. Finally, register content is
the CRC values for all characters in the frame.

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