Camera Interface
BASLER L304
kc 2-13
Draft
Operation in 2 Tap 10 Bit or 2 Tap 8 Bit Output Modes
In 2 tap 10 bit output mode, L304kc cameras operate with a 60 MHz pixel clock. On each clock
cycle, the camera transmits data for two pixels at 10 bit depth, a line valid bit and a data valid bit.
The assignment of the bits is as shown in Table 2-3.
The Camera Link pixel clock is used to time data sampling and transmission. As shown in Figures
2-6 and 2-7, the camera samples and transmits data on each rising edge of the pixel clock. The
line valid bit indicates that a valid line is being transmitted and the data valid bit indicates that valid
pixel data is being transmitted. Pixel data is only valid when the line valid and data valid bits are
both high.
Operation in 2 tap 8 bit mode is similar to 10 bit mode except that the two least significant bits are
dropped and only 8 bits of data per pixel are transmitted.
Video Data Sequence
1
When the camera is not transmitting valid data, the line valid and data valid bits transmitted on
each cycle of the pixel clock will be low. Once the camera has completed line acquisition, it will
begin to send valid data:
• On the clock cycle where pixel data transmission begins, the line valid and data valid bits will
become high. The 10 “Pixel A” bits transmitted during this clock cycle will contain the data for
pixel number one in the red line and the 10 “Pixel B” bits will contain the data for pixel number
one in the green line.
• On the second cycle of the pixel clock, the line valid and data valid bits will be high. The 10
“Pixel A” bits transmitted during this clock cycle will contain the data for pixel number one in
the blue line and the 10 “Pixel B” bits will contain dummy data and should be ignored.
• On the third cycle of the pixel clock, the line valid and data valid bits will be high. The 10
“Pixel A” bits transmitted during this clock cycle will contain the data for pixel number two in
the red line and the 10 “Pixel B” bits will contain the data for pixel number two in the green
line.
• On the fourth cycle of the pixel clock, the line valid and data valid bits will be high. The 10
“Pixel A” bits transmitted during this clock cycle will contain the data for pixel number two in
the blue line and the 10 “Pixel B” bits will contain dummy data and should be ignored.
• This pattern will continue until all of the pixel data for the line has been transmitted. (A total of
8160 cycles.
2
)
• After all of the pixels have been transmitted, the line valid and data valid bits will become low
indicating that valid pixel data is no longer being transmitted.
____________________
1
The data sequence assumes that the camera is operating in 10 bit mode. If the camera is
operating in 8 bit mode, only 8 bits of data per pixel will be transmitted.
2
When the AOI and Counter Stamp features are used, the number of cycles could be more or less
than 8160. See Sections 3.7 and 3.8 for more information.
L
The data sequence outlined below, along with Figures 2-6 and 2-7, describe what is
happening at the inputs to the Camera Link transmitter in the camera.
Note that the timing used for sampling the data at the Camera Link receiver in the
frame grabber varies from device to device. On some receivers, data must be sam-
pled on the rising edge of the pixel clock (receive clock) and on others, it must be
sampled on the falling edge. Also, some devices are available that allow you to se-
lect either rising edge or falling edge sampling. Please consult the data sheet for the
receiver you are using for specific timing information.
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