Table 5-3:
D11A
and Audio Channel Enable Bits
DMACON
Register
Bit
Name
Function
15
SETCLR
When this bit is written as a
1,
it
sets any bit
in
D11ACONW for which
the corresponding bit position is
also a
1,
leaving all other bits alone.
9
D11AEN
Only while this bit is a
1 can
any
direct memory access occur.
3
. AUD3EN
Audio channel 3 enable .
2
AUD2EN
Audio channel 2 enable.
1
AUDIEN
Audio channel
1 enable.
0
AUDOEN
Audio channel 0 enable.
For example,
if
you are using channel
0,
then you write a 1 into
bit
9 to enable
D11A
and a 1 into bit 0 to enable the audio channel, as shown below.
SET
EQU
AUDOEN
EQU
D11AEN EQU
BEGINCHANO:
$08000
$01
$0200
MOVE.W
#(SET
+
AUDOEN
+ D11AEN), D11ACONW
STOPPING
THE
AUDIO
DMA
You can stop the channel by writing a 0 into the AUDxEN bit
at
any time. However,
you cannot resume the
output
at
the same point
in
the waveform by
just
writing a 1
in
the bit again. Enabling an audio channel almost always
starts
the
data
output
again
from the top of the list of
data
pointed to by the location registers for
that
channel. If
the channel
is
disabled for a very short time (less than two sampling periods) it may stay
on and thus continue from where it left
off.
144 Audio Hardware