Commodore Amiga - Bit-Plane;Processor Bus Sharing; Figure 6-12 Normal 68000 Cycle

BIT.PLANE/PROCESSOR BUS SHARING
The 68000 uses only the even-numbered memory access cycles. The 68000 spends about
half of a complete processor instruction time doing internal operations and the other half
accessing memory. Therefore, the allocation of alternate memory cycles
to the 68000
makes it appear to the 68000
that it has the memory all of the time, and it will run at
full speed.
Some 68000 instructions do not match perfectly with the allocation of even cycles and
cause cycles
to be missed. If cycles are missed, the 68000 must wait until its next avail-
able memory slot before continuing. However, most instructions do not cause cycles
to
be missed, so the 68000 runs at full speed most of the time if there is no blitter DMA
interference.
Figure 6-12 illustrates the normal cycle of the 68000.
average 68000 cycle
internal memory
operation
access
portion portion
odd cycle, even cycle,
assigned to available to
other devices
the 68000
Figure 6-12: Normal 68000 Cycle
If the display contains four or fewer low-resolution bit-planes, the 68000 can be granted
alternate memory cycles (if it
is ready to ask for the cycle and is the highest priority
item
at the time). However, if there are more than four bit-planes, bit-plane DMA will
begin
to steal cycles from the 68000 during the display.
During the display time for a six-bit-plane display (low resolution, 320 pixels wide), 160
time slots will be taken by bit-plane DMA for each horizontal line. As you can see from
figure 6-13, bit-plane DMA steals 50 percent of the open slots
that the processor might
have used if there were only four bit-planes displayed.
Blitter Hardware
189