Commodore Amiga - Page 199

o 4 cycles for memory refresh (assigned to odd-numbered slots)
o 3 cycles for disk
D:MA
o 4 cycles for audio D11A (2 bytes per channel)
o 16 cycles for sprite D11A (2 words per channel)
o 80 cycles for bit-plane
D11A (even- or odd-numbered slots according to the
display size used)
Figure
6-11 shows one complete horizontal scan line and how the clock cycles are
allocated.
Blitter Hardware
187