Commodore Amiga - Page 204

Table 6-4: Typical Blitter Cycle Sequence
USE Code
in
Active
BLTCONO
Channels
Cycle Sequence
F
A B 0
D
AO
BO 00
-
Al
Bl 01
DO
A2 B2 02
Dl
D2
E A
B 0
AO BO
00
Al Bl
01
A2
B2 02
D A
B D
AO BO
-
Al
Bl
DO
A2
B2 Dl
-
D2
0 A
B
AO BO
-
Al Bl
-
A2 B2
B A
0 D
AO 00
-
Al 01
DO
A2 02 D1
-
D2
A A
0
AO 00
Al
01 A2 02
9
A
D
AO
-
AI DO
A2 Dl
-
D2
8 A
AO
-
Al
-
A2
7
B 0 D
BO 00
-
Bl
01
DO
-
B2 02 Dl
-
D2
6
B 0
BO 00
-
Bl 01
-
B2 02
5
B D
BO
-
Bl DO
-
B2 Dl
-
D2
4
B
BO
-
Bl
-
B2
3
0 D 00
-
01 DO
-
02 Dl
-
D2
2
0
00 -
01
-
02
1
D
DO
-
Dl
-
D2
0
none
Notes for table 6-4:
o No fill.
o No competing bus activity.
o Three-word blit.
o Typical operation involves fetching all sources twice before the first destination
becomes available. This is due
to internal pipelining. Care must be taken with
overlapping source and destination regions.
Table 6-4
is only meant to be an illustration of the typical order of blitter cycles on the
bus. Bus cycles are dynamically allocated based on blitter operating mode; competing
bus activity from processor, bit-planes, and other DMA channels; and
other factors.
Commodore-Amiga does not guarantee the accuracy of or future adherence
to this chart.
We reserve the right
to make product improvements or design changes in this area
without notice.
192 Blitter Hardware