See chapter
5,
"Audio Hardware," for more information about interrupt generation and
timing.
Blitter
Interrupt
Bit
6,
BLIT, signals "blitter finished."
If
this bit is a
1,
it indicates
that
the blitter has
completed the requested
data
transfer.
The
blitter is now ready
to
accept another task.
This bit generates a level 3 interrupt.
Disk
Interrupt
Bits
12
and 1 of the interrupt registers are assigned to disk interrupts.
Bit
12,
DSKSYN, indicates
that
the sync register matches disk data. This bit generates
a level 5 interrupt
Bit
1,
DSKBLK, indicates "disk block finished."
It
is used to indicate
that
the specified
disk DMA task
that
you have requested has been completed. This bit generates a level 1
interrupt.
More information about disk
data
transfer and interrupts may be found in chapter
8,
"In
terf ace Hard ware. "
Serial
Port
Interrupts
The
following serial interrupts are associated with the specified bits of the interrupt
registers.
Bit
11,
RBF (for receive buffer full), specifies
that
the input buffer of the UART has
data
that
is ready to read. This bit generates a level 5 interrupt.
Bit
0,
TBE (for "transmit buffer empty"), specifics
that
the
output
buffer of the UART
needs more
data
and
data
can now be written into this buffer. This bit generates a level
1 interrupt.
System Control Hardware
211
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