Table 7-6: Contents of DMA Register
Bit
Number
Name
Function
15
SET/CLR
The
set/reset
control bit. See description
of
bit
15 under
"Interrupts"
above.
14
BBUSY
Blitter busy
status
- read-only
13
BZERO
Blitter zero
status
- read-only. Remains 1
if,
during a blitter operation, the blitter
output
was always zero.
12,11
Unassigned
10
BLTPRI
Blitter priority. Also known as "blitter-nasty."
When this is a 1, the blitter has full (instead of
partial) priority over
the
68000.
9
DMAEN
DMA enable. This is a master DMA enable bit.
It
enables the DMA
fol'
all of
the
channels
at
bits 8-0.
8 BPLEN
Bit-plane DMA enable
7
COPEN
Coprocessor DMA enable
6
BLTEN Blitter DMA enable
5
SPREN
Sprite DMA enable
4
DSKEN Disk DMA enable
3-0 AUDxEN Audio DMA enable for channels 3-0 (x
= 3 - 0).
For
more information on using the DMA, see the following chapters:
Sprites - chapter 4, "Sprite Hardware"
Bit-planes - chapter
3,
"Playfield Hardware"
Blitter - chapter
6,
"Blitter Hardware"
Disk - chapter 8, "Interface Hardware"
Audio - chapter
5,
"Audio Hardware"
Copper - chapter
2,
"Coprocessor Hardware"
System Control Hardware 213
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