Commodore Amiga - Page 258

Read/
Register Address write
Agnus/
Denise/
Paula Function
AOKCON
ADKCONR
AUDxLCH
AUDxLCL
AUDxLEN
09E
010
W
R
P Audio, disk, control write
P Audio, disk, control read
BIT# USE
15 SET/CLR Set/clear control bit. Determines if bits
written with a 1 get set or cleared. Bits
written with a zero are always unchanged.
14-13 PRECOMP 1-0 CODE PRECOMP VALUE
12 MFMPREC
11 UARTBRI<
10 hURDSYNC
00 none
01 140 ns
10 280 ns
11 560 ns
( l=MFM precorrp O=CX:R preconp)
Forces a UART break (clears TXO) if true.
Enables disk read synchronizing on a word
equal to DISK SYNC CODE, located in
address (3F) *2.
09 MSBSYNC Enables disk read synchronizing on the MSB
(most signif bit) . Appl type OCR.
08 FAST Disk data clock rate control 1=fast(2us) 0=slow(4us).
(fast for MFM, slow for MFM or OCR)
07 USE3PN Use audio channel 3 to modulate nothing.
06 USE2P3 Use audio channel 2 to modulate period of channel 3.
05 USE1P2 Use audio channell to modulate period of channel 2.
04 USEOP1 Use audio channel 0 to modulate period of channell.
03 USE3VN Use audio channel 3 to modulate nothing.
02 USE2V3 Use audio channel 2 to modulate volume of channel 3.
01 USE1V2 Use audio channell to modulate volume of channel 2.
00 USEOV1 Use audio channel 0 to modulate volume of channel 1.
NOTE: I f both period and volume are modulated on the
same channel, the period and volume will be alternated.
First word xxxxxyyx V6-VO , Second word PIS-PO (etc)
OAO W A Audio channel x location (high 3 bits)
0A2 W A Audio channel x location (low 15 bits)
This pair of registers contains the 18 bit starting address
(location) of audio channel x (x=O,l,2,3) DMA data.
This is not a pointer register and therefore needs
to be reloaded only if a different memory location 1s to
be outputted.
OA4 W P Audio channel x length
This register contains the length (number of words) of
audio channel x DMA data.
AUDxPER
AUDxVOL
AUDxDAT
BLTxPTH
BLTxPTL
BLTxK>D
OAG W P Audio channel x Period
OAB
This register contains the period (rate) of
audio channel x DMA data transfer.
The minilmlm period is 124 color clocks. This means
that the smallest nwnber that should be placed in
this register is 124 decimal. This corresponds to
a maxilmlm sanple frequency of 28.86 khz.
W P Audio channel x volume
This register contains the volume setting for
audio channel x. Bits 6,5,4,3,2,1,0 specify 65
linear volume levels as shown below.
Bit# Use
15-07
06
05-00
Not used
Forces volume to max (64 ones, no zeros)
Sets one of 64 levels (OOOOOO=no output
(111111=63 Is, one 0)
OAA W P Audio channel x data
This register is the audio channel x (x=O,l,2,3)
DMA data buffer. It contains 2 bytes of data that
are each 2' s corrplement and are outputted
sequentially (with digital-to-analog conversion)
to the audio output pins. (LSB = 3 MY) The DMA
controller automatically transfers data to this
register from RAM. The processor can also write
directly to this register. When the DMA data 1s
finished (words outputted=length) and the data in
this register has been used, an audio channel
interrupt request is set.
050 W A Blitter pointer to x (high 3 bits)
052 W A Blitter pointer to x (low 15 bits)
This pair of registers contains the 18-bit address
of blitter source (x=A,B,C) or destination (x=D)
DMA data. This pointer must be preloaded with the
starting address of the data to be processed by
the blitter. After the blitter is finished, it
will contain the last data address (plus increment
and modulo).
LINE DRAW BLTAPTL is used as an accumulator
LINE DRAW register and II1lSt be preloaded with
LINE DRAW the starting value of (2Y-X) where
LINE DRAW Y/X is the line slope. BLTCPT and
LINE DRAW BLTDPT (both H and L) must be
LINE DRAW preloaded with the starting address
LINE DRAW of the line.
064 W A Blitter modulo x
This register contains the modulo for blitter
source (x=A,B,C) or destination (x=D). A modulo
is a number that is automatically added to the
address at the end of each line, to make the