Commodore Amiga - Page 276

ADDRESS RANGE NOTES
000000-03EEEF 256k bytes. of RAM
040000-07FEEF 256k bytes of di~lay RAM (option card)
080000-lFEEFF Do not use
200000-9EEEFF ~l ~ansion ~ace
AOOOOO-BEEEFF Do not use
BEDOOO-BEDEOO 8520-B (access only at EVEN byte addresses)
= =
BEE001-BEEE01 8520-A (access only at ODD byte addresses)
= =
The underlined digit chooses which of the
16 internal registers of the 8520 is to be
accessed.
Register names are given below.
COOOOO-DEEEEF
DEEOOO-DEEFFF
EOOOOO-E7FEFF
E80000-EEEEEF
FOOOOO-E7FEEF
F80000-EEEEEF
Reserved for future use
Special purpose chips, where
the last three digits specify
the chip register hURD address.
The chip addresses are specified
in separate pages inmediatel y
following
this overall memory map.
Reserved for future use - do not use
Expansion slot decoding
Reserved - do not use
System RC»f
DEVELOPMENT SYSTEM ROMs located at start address FEOOOO
FINAL SYSTEM ROMs will probably be located at FeOOOO
The names of the registers within the 8520s are
as follows. The address at which each is to be
accessed is given in this list.
Address for:
8520-A 8520-B I NAME I EXPLANATION
-------------------------------------------------
BEE001
BEE101
BEE201
BEE301
BEE401
BEE501
BEE601
BEE701
BEE801
BEE901
BEEA01
BEEB01
BEEeOl
BEEDOl
BEEE01
BEEE01
BEDOOO
BEDlOO
BED200
BED300
BED400
BEDSOO
BED600
BED700
BEDSOO
BED900
BEDAOO
BEDBOO
BEDCOO
BEDDOO
BEDEOO
BEDEOO
PRA
PRB
DDRB
DDRA
TALO
TAHI
TBLO
TBHI
SDR
ICR
CRA
CRB
(write) / (read mode)
Peripheral data register A
Peripheral data register B
Data
direction register A
Data
direction register B
TIMER A low register
TIMER A high register
TIMER B low register
TIMER B high register
Event LSB
Event 8 - 15
Event
MS8
No connect
Serial data register
Interrupt control register
Control register A
Control register B