30 3 Interface
1.8 Signal Timing Charts
Leak Test Timing Chart
*1 CH # includes CH #, K(Ve) CHECK, MASTERING / DRIFT CLR, and Calibration Valve Open/Close signals.
*2 JUDGMENT includes PASS, UL FAIL, LL FAIL, UL2 FAIL AND LL2 FAIL signals.
Mastering Timing Chart
*1 MASTERING REQUEST signal is an output signal.
*2 MASTERING/DRIFT CLEAR signal is an input signal.
CH#
MASTERING REQUEST
*1
MASTERING / DRIFT CLEAR *2
START
BUSY
300ms
(MIN.)
400ms(MIN.)
300ms(MAX.)
100ms(MIN.)
300ms
(MAX
.)
300
ms(
MIN
.)
400ms(MIN.)
300ms(MAX.)
DL1
PCHK
CHG
BAL1
BAL2
DET
BLW
EXH
END
WAIT
WAIT
"0"
"1"
"2"
"3"
"1""2"or"3"
for Fail only
"0"
100ms(MIN.)
ERROR
CH# *1
START
BUSY
STAGE #
END
JUDGMENT *2
DL2