CURTISS-WRIGHT PRODUCT OVERVIEW
826448 VERSION 5 MARCH 2015 PROPRIETARY 1-13
The Core Functions FPGA provides a set of internal resources and interfaces to external
devices accessible by the processor on the board. Each processor node accesses the FPGA with
a Low Pin-Count (LPC) bus through its associated Platform Controller Hub (PCH). The FPGA
connects to the two LPC buses through two Local Processor Blocks (LPB). In addition to the
LPC interface function, the LPB contains a set of resources unique to the node that are
inaccessible to the other node. The Processor Interface Block (PIB) arbitrates and passes
transactions from the LPC bus to the shared resources. The PIB acts as a switch fabric between
the LPB and the shared resources. The shared resources accessible by all nodes are located in
the Project Specific resources Block (PSB), the Utility Block (UB), System Monitor, I2O, and
SHMUART.
I2O Block The CHAMP-AV8 includes an I2O block. There are four separate I2O modules in the I2O block
(one per processor core).
Each module consists of:
• Inbound Doorbell Register
• Inbound Buffer Free Queue
• Inbound Buffer Post Queue
• Outbound Message Register
The I2O Inbound Doorbell Registers send and receive short messages between CPUs with
access to global memory space. Each I2O unit has four 32-bit Inbound Doorbell Registers,
each assigned to an owner CPU. The owner CPU for each register is software-configurable. This
allows other CPUs in the fabric to communicate directly with the owner. Writing to an Inbound
Doorbell Register causes an interrupt request to the owner CPU. As with the Doorbell
Registers, there are four 32-bit Inbound Message Queues, each with an owner. Each queue
holds 512 messages. The Inbound Post Queue holds posted messages from the fabric to owner
CPUs. The owner CPU fetches the next message process from the queue tail; a CPU posts
messages to the queue head. The Inbound Free Queue holds available inbound free messages
(data buffer addresses) for CPUs to use. The owner CPU places free messages at the queue
head; CPUs fetch free messages from the queue tail. The outbound message register is simply
a 32-bit register used by the owner CPU to advertise his Processor ID to the rest of the fabric.
The owner CPU writes this register and the non-owner reads it.
DOUBLE DATA RATE (DDR3) SDRAM WITH ECC
Each processor node on the CHAMP-AV8 supports up to 4GB of DDR3 SDRAM for a total of
8GB on the board. Each processor features two DDR3 memory channels. With two channels
of DDR3-1333, each processor achieves a peak memory bandwidth of over 21GB/s. The
memory is protected with Error Checking and Correcting (ECC) circuitry that can detect and
correct all single-bit errors and detect all double-bit errors.
The memories reside on a separate module, one per node, and connect to the base board via
stacking connectors.
Consult the factory for updated information on the availability of the 8GB variant of the
CHAMP-AV8.
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